Nanoelectronics

The current state:  Moore's Law and physical limitations
Co-founder of Intel, Gordon Moore, made a prediction in 1965 about the development of transistors for processor chips.   Moore's Law as it is now formally known says that the number of transistors on an integrated circuit doubles every two years.   A graph of Moore's Law shows how the number of transistors have increased since the inception of Intel's first microprocessor, which contained just 2200 transistors.   Gordon Moore said that "the first microprocessor only had 22 hundred transistors. We are looking at something a million times that complex in the next generations — a billion transistors. What that gives us in the way of flexibility to design products is phenomenal."   As more transistor are crammed into circuits, the cost per transistor decreases, but the rate of defective circuits also increases, creating complexity to the total cost.   Moore's Law does not just involve the quantity of transistors, but also the quantity of transistors at which the minimum cost is maintained.   Advances in photolithography in recent years have allowed intel to venture from conventional 90 nm transistors to 60 nm and, most recently, 45 nm transistors. Smaller transistors have a definite advantage over larger transistors in processing speed.   Smaller terminals on transistors allow the transistors to switch between on and off states faster.   However, continuing to push silicon integrated circuits down to the nanolevel presents problems, particularly in the area of heat.   As more transistors are packed into a chip, the amount of heat produced from the circuitry also increases, and the chip is more prone to failure.  

The need for nano:  benefits to downsizing with nanomaterials
Nanotechnology research has focused on ways to make transistors smaller as well as to develop different transistors, such as the single-electron transistor (SET). Using nanomaterials and other nanotechnology concepts with transistors has several benefits:

•  Higher transistor density — The obvious benefit to downsizing with nanomaterials is that the dimensions will be smaller than transistors on processors currently in the market.   Therefore, more transistors can be made on a processor.
•  Reduced heat production — The excellent thermal properties of nanotubes is vital to increasing the density of transistors.   Imagine having a smaller, more powerful processor that have no need for heat sinks or fans.  
•  Less power consumption — The electrical properties of nanomaterials enable transistors to perform tasks more efficiently.   Higher density silicon chips result in more power consumption, but recent advances with nanotube MOSFETs and SETs will benefit battery life.  

The MOSFET scaled down
Two different three-terminal semiconductor devices are used in electronics: the bipolar junction transistor (BJT) and the metal-oxide-semiconductor field-effect transistor (MOSFET).   In the area of integrated circuit design, MOSFETs are chosen over BJTs because they can be made smaller and they are more efficient in terms of power.   Also, the relatively simple process used to produce MOSFETs minimizes cost.   To grasp the functionality of nanoscale transistors, consider the layout and operation of a conventional MOSFET.

• MOSFET layout
  A MOSFET contains three terminals — a source, drain ,and a gate.   As suggested by the name, the source is where the charge carriers enter the current channel in route to the drain, while the drain is the location where the charge carriers exit the channel.   The gate acts to allow or inhibit the flow of current from the source to the drain.   If the charger carriers in the transistor are electrons, the MOSFET is known as n-channel or NMOS, and if holes are the dominating charge, it is labeled as p-channel or PMOS.   In an n-channel MOSFET, the silicon substrate is doped to be p-type, indicating the presence of holes in the substrate.   The two regions below the source and drain terminals are heavily doped (indicated by the '+' sign) to from n-type sections in the substrate.   The regions below the source and drain must be of the same type, yet different than the substrate.   An insulating oxide (usually SiO2) spans the regions from the source to the drain.   The gate terminal is metal grown on the oxide so that the oxide separates the gate from the source and drain regions of the substrate.   A metal is also used for the terminals of the source, drain, and the body of the substrate.   A PMOS transistor will have regions doped exactly opposite that of the NMOS.   The substrate is n-type silicon and the source and drain are heavily-doped p-type regions.   The insulation of the gate from the source, drain, and substrate is instrumental in the operation of the MOSFET.  
  
  
• MOSFET operation
  Consider a positive voltage placed across the gate and source terminals of an NMOS transistor.   The positive charges collected on the bottom of the gate terminal interacts with other positive charges in the substrate, due to the close proximity.   Since like charges repel each other, the positive charges in the substrate are driven lower into the substrate.   The result of the hole movement is an increased number of electrons around the top of the substrate in what is known as the depletion region.   The depletion of holes from the top of the substrate induces a small n-type channel between the source and drain.   The connection of the source and drain through the channel permits the flow of current.   If the drain voltage relative to the source voltage (i.e. VDS) is positive, then current can flow between the source and drain.   Following the current convention where current is the movement of holes, the current flows through the n-channel from the drain to the source.   Turning off the gate voltage causes the depletion region to revert back to its original p-type, which in turn causes the channel to disappear and the current to cease.   The amount of current which can flow through the the channel is determined by the gate-source voltage, VGS.   As VGS increases, more positive charges agglomerate at the bottom of the gate terminal's metal electrode.   The voltage at which enough electrons gather between the source and drain to form the channel connection is known as the threshold voltage of the MOSFET, or Vt.   The threshold voltage varies between each transistor because it is based on the intrinsic physical qualities of the device.   The combination of the positive charges in the gate, the oxide layer acting as a dielectric, and the negative charges in the n-channel forms a capacitor with a vertical electric field through the insulator.   Increasing VGS past the threshold voltage induces more negative charges in the channel.   In the presence of a drain-source voltage, then, more negative charges in the channel increase the current through the channel.   Therefore, the current through the transistor is dependent on both the gate-source voltage in relation to the threshold voltage and the drain-source voltage.   The drain-source voltage effects the depth of the channel between the source and drain.   In particular the depth of the channel is related to (VGS - VDS). A drain-source voltage at or above the overdrive voltage causes the channel to be pinched off at the drain.   A pinched channel has the effect of saturating the current regardless of the further increase of VDS. As with other electronic devices, a current-voltage or I-V characteristic is important in determining how the device actually operates.   For example, if the gate-source voltage is not sufficiently above the threshold voltage of the MOSFET, then the channel will be cutoff and no electrons will flow between the source and drain.   However, if the gate-source voltage is above the threshold, and the drain-source voltage is too small to pinch the channel, then the channel depth will vary depending on the magnitude of VDS.   A smaller channel depth causes the impedance to increase in the channel towards the drain; therefore, the current will aslo change with these voltage conditions.   The application of a small VDS causes the drain current to exhibit linear changes, but as the channel gets closer to the pinch off point, the current gradually saturates.   The I-V characteristic of the MOSFET shows three modes of operation, which have been described above.   Two equations are used to describe the behaviour of the I-V characterstic.   The equation for the triode region is parabolic in nature and must depend on both the overdrive voltage as well as the drain-source voltage since the channel is not pinched.   Once saturation occurs, the triode region's equation is no longer valid becuase the effect of the drain-source voltage on the channel is minimal.   The equation for the current in the saturation region relates the drain current to the overdrive voltage, which is just a constant value if VGS is unchanging.   The boundary between the saturation and triode regions varies as the overdrive voltage increases and is given by VDSsat = VGS - Vt.  
  
  The physical dimensions of the MOSFET play a key role in device parameters and operation.   Changing the width and type of insulating layer between the gate electrode and the channel alters the strength of the electric "field effect" experienced in the channel.   The process transconductance parameter in the current-voltage equations is a constant reflecting the type of technology used in the development of the transistor as well as the influence of oxide dimesions.   The length and width of the channel, denoted by L and W in the current-voltage equations, is a primary focus of scaling down the MOSFET.   The smaller the channel can be made without hurting thermal performance and electrical characteristics, the faster the transistor will operate.   However, many difficulties present themselves when fabricating smaller conventional silicon-based transistors.   To achieve a shorter channel, the source and drain regions on the substrate need to be closer together.   As a result of the relocation, the oxide layer also must be made thinner.   Currently, the oxide is just above a mere 1 nm thick.   Making the layer any thinner than that and the transistor is subject to breakdown via a quantum phenomenon known as tunneling.   In other words, the insulating layer no longer insulates, and the gate cannot perform its function of enabling and disabling the current through the channel.   Another downside of smaller dimensions is that the input voltage also needs to decrease.   If insufficient voltage is applied to the gate, there is a risk that the transistor may not fully turn on.  
  
  The highly researched carbon nanotube FET (CNTFET) is the device which many believe to be the answer to the problems of conventional silicon-based integrated circuits.   The goal of research with the CNTFET is obtaining stable operation characterstics similar to the I-V characteristic discussed above for current FET technology.   In the world of digital integrated circuits, it is important for MOSFETs to operate in the saturation region so that digital high (1) and low (0) values can be observed.   So, researchers seek to find CNTFET constructions which result in experimental data that is on par or better than silicon FETs.   The CNTFET is still a three terminal device with a gate, drain, and source, but the only major difference between existing FET technology and the CNTFET is that the channel is a well-placed semiconducting carbon nanotube.   IBM's research under Phaedon Avouris led to the development and testing of one of the first versions of a CNTFET.   The carbon nanotube was placed on top of the insulating oxide layer and spans the distance between the source and drain to form the channel.   A side view of the initial CNTFET shows a bending of the nanotube.   More sophisticated CNTFETs being researched today resemble a MOSFET with the gate electrode and oxide placed above the nanotube channel, which is still connected on either end by the source and drain metal electrodes.   Results from testing at IBM revealed that the CNTFET can indeed act like a normal MOSFET.   The application of a sufficient amount of voltage to the gate electrode caused the nanotube to conduct current, turning the transistor on.   Removing the voltage blocked the current to turn off the transistor.   However, upon further testing, researchers found that the CNTFET operated differently than the MOSFET.   In the MOSFET, the strength of the gate voltage changed the induced channel's electrical properties to cause variable amounts of conductance.   The nanotube in the CNTFET is a permanent channel, so the gate voltage does not need to induce a channel.   Variation of the gate voltage on the CNTFET does not change the actual electrical properties of the nanotube channel.   Instead, the switching attributes of the transistor occur in the junctions between the nanotube and the drain and source electrodes, which are metal.   The junction between between a metal and semiconductor is known as a Schottky barrier.   An increase in the magnitude of the gate voltage alters the energy levels at the metal-semiconductor junction to decrease the width of the Schottky energy barrier.   As the barrier width decreases, electrons (or holes if they are the majority carrier) have a greater chance of tunneling through the barrier from the semiconductor to the metal or vice versa.   The same quantum mechanical phenomenon of tunneling which can cause silicon integrated circuits to breakdown allows the CNTFET to perform as a transistor.  
  
  Another type of I-V characteristic used in FET analysis is the channel current (or drain-source current) with respect to variations in the gate voltage under certain drain-source voltage bias.   In the previously discussed I-V characteristic, the gate voltage was held constant while the drain-source voltage was varied.   This IDS-VDS plot is useful for seeing the FET's saturation.   The IDS-VGS characteristic, on the other hand, is more useful for analyzing the FET's operation as a switch.   Experiments show how the CNTFET can operate as a switch given a certain drain-source voltage.  
  
  

The semiconductor industry and chip fabricaton on the nanoscale
With the semiconductor IC industry trying to keep the pace of Moore's Law, scaling down the transistor and overall chip size presents more problems than just heat and stray signals.   The actual production techniques need to have the ability to create the increasing density of transistors.   The most widely used process used to create the patterns of transistors on a substrate is known as photolithography. However, the process is painstaking — the production time is long and the operating conditions in which the chips are developed are extreme.   A single chip can take as long as two weeks from start to finish, and the work environment needs to pristine.   The air in the production facility, for example, is changed about ten times in the span of minute to rid the environment of any possible dust which can ruin a chip.   The painstaking process likely will not change much when newer methods are introduced, but the cost effectiveness may be improved.   Even though transistors and the resulting processor become faster when decreased in size, the cost of production also increases.   Nanotechnological tweaks to existing top-down methods as well as new bottom-up applications of nanotechnology may prove to be an answer to leveling rising cost while reducing the chip size.  

• Current photolithography technology
  As the name suggests, photolithography is a method which uses light to write or print patterns on a material.   The process contains several steps.
  
  
  • Cut a silicon ingot into silicon wafers:   An ingot is a long silicon crystal which can be grown with various sizes.
  • Coat the wafer with silicon dioxide:   Wafers are exposed to high temperatures while in a chamber.   As gas moves over the silicon substrate, the surface reacts with the oxygen in the gas to form SiO2.
  • Coat the wafer with photoresist:   The photoresist is a material which can either soften or harden when exposed to ultraviolet (UV) light to become more or less soluble.   A negative photoresist becomes less soluble upon light exposure, while a positive photoresist becomse more soluble.   The resist is applied evenly by spinning the wafer under a stream of liquid resist.  
  • Shine the light through a mask to imprint a circuit on the photoresist:   The mask is similar to a stencil.   Certain sections of the mask allow light to pass, while the rest of the body of the mask absorbs the light.  
  • Wash off the soluble photoresist with a chemical solvent:   The areas that are washed away leave the silicon dioxide as the top surface instead of the photoresist.   The insoluble areas of the photoresist remain atop the other sections of silicon dioxide.  
  • Etch away the silicon dioxide to form the same circuit pattern on the silicon:   Etching, much like the photoresist solvent, removes just the silicon dioxide with chemicals to expose the underlying silicon.   The remaining photoresist is untouched.   (When creating a transistor, elements are implanted into the silicon layer after this step for the purpose of creating n-type or p-type sections.   Elements from group III are used for acceptor impurities, while a group V element is used for a donor impurity.   The acceptor impurity will take an electron from the valence band to form a hole for conduction.   Likewise, the donor impurity donates an electron to the conduction.)
  • Remove the remaining photoresist through additional solvents:  
  
  In addition to the steps, metal must also be added to form the electrodes of the source, drain, and gate, which complete the transistor.   The process must be repeated many times with different masks to achieve the desired integrated circuit.  
  
  
• Techniques with promise for nanotechnology
  Since the minimium feature size on a chip depends on the wavelength of light used in photolithography, changing the light source will also change the size and clarity of the image projected onto the wafer.   Decreasing the wavelength will decrease the feature size.   Deep ultraviolet (DUV) light with wavelengths of 248 nm, 193 nm, and 157 nm are used in current photolithography instruments to obtain feature sizes ranging from 200 nm down to 50 nm.   However, going even deeper into the ultraviolet spectrum, instruments using extreme ultraviolet (EUV) light with wavelengths between 10 and 14 nm are being researched and tested.   The process using EUV light is still the same as that which uses DUV light, but some of the instrument's components must change.   The problem is that EUV light is absorbed by many different materials.   The lens used in the typical photolithography process, for example, absorbs the EUV light, so none of the EUV light will be focused onto the wafer.   One way which researchers have explored to hurdle this difficulty is to use mirrors (made of a material which does reflect EUV light) to focus the light at a location on the wafer.   However, the mirrors present an arguably more difficult problem of precision.   The material used for the photoresist also must change.   The photoresist responds differently to the EUV light than the DUV light, so the photoresist cannot perform its function.   By chaning the photoresist, the etching process may be negatively affectted.   The photoresist must be very resilient to the etching process to keep good crisp boundaries between doped regions and undoped regions.  
  
  A bottom-up approach:  self-assembly
  
  Nanomaterials and strucutres can be developed through either a top-down or bottom-up approach.   Things such as photolithography are viewed as top-down techniques because ultraviolet light is used us to chip away a large material to make a smaller component.   A bottom-up approach is important to nanotechnology because it will allow for smaller, more precise materials.   Richard Feynman's speech entitled "There's Plenty of Room at the Bottom" given in 1959 at Caltech foreshadowed future technology which could manipulate individual atoms, namely atomic force microscopes (AFM) and scanning tunnelling microscopes (STM).   Even though AFMs and STMs are instrumental in research and can develop structures from the bottom up, they cannot be scaled up to form many components part of a larger system.   The process would be too tedious since atoms are placed in a serial fashion and not simultaneously.   In search of something that can assemble nanostructures quickly from the bottom-up, look no further than the building block of life:  DNA.   Over the last fifty years since the discovery of the structure of DNA by Watson and Crick, enormous amounts of study have gone into the function and applications of DNA in biology.   Recently in the past several years, though, researchers have found that DNA can be exploited to perform functions no other molecule can achieve.   The field of DNA nanotechnology takes advantage of the unique properties of DNA to create predictable yet complex nanostructures.   One of the major well-known benefits of DNA is the fact that it self-assembles under normal conditions (as opposed to clean rooms or subzero temperatures).   The nucleotides (adenine, thymine, guanine, and cytosine) pair up, adenine with thymine and guanine with cytosine, to bring together two complimentary strands of DNA into the double helix strucutre.   By controlling the arrangment of nucleic acids along the strands of DNA in a solution, a host of nanostructures, both planar and 3-D, can be created.   To understand how DNA can be manipulated into forming complex materials, three concepts should be considered:  the sticky end, branched DNA, and the double crossover.   A sticky end is a strand of DNA which has unpaired nucleotides at one of its ends, extending beyond the double helix.   A second DNA strand with the correct complimentary nucleotide sequence on its sticky end can then connect with the first DNA strand.   Any other sequence will prevent the DNA strands from binding.   Thus, sticky ends are used to selectively choose which strands can combine.   The most common form of DNA and the type which is used most frequently in nanotechnology is B-DNA.  
  
  The sticky ends of DNA play a crutial part in branched DNA.   Branched DNA has been observed as a result of cell reproduction, but it has also been recreated using synthetic DNA.   After unwinding and replicating, DNA recombines into its double helix form.   However, it is quite possible that damage causes the DNA to break along its axis and to remain partially unvraveled.   At one end, the DNA is normal and intact, but the other end acts like two longer version of sticky ends.   If two double helices break, then the single-stranded portions of each of the broken helices may combine to form a four-way junction or branch point (four arms, each being a double helix).  The difference between branched DNA resulting from recombination in the cell and synthesized branched DNA is the mobility of the branch point.   In the cell, the branched DNA orginates from B-DNA; therefore, the single stranded portions have no trouble combining since they are completely complementary.   The symmetry between each of the helices in natrual DNA allows the branch point to vary its position along the strands.   With synthesized branched DNA, the branch point is fixed due to a lack of symmetry, but this fixation is not usually seen as a disadvantage.   With the application of sticky ends to branched DNA, other junctions with complemetary sticky ends can attach to each of the arms to create a highly ordered array of DNA.  
  
  Branched DNA demonstrates how 2-D patterns can be created with DNA, but more complex structures can be created through the double crossover (DX).   The double crossover is another way of adjoining sections of DNA building blocks.   Like branched DNA, the double crossover is a phenomenon which also occurs during cellular reproductions and recombination.   The double crossover is an intertwining of two adjacent helices where a single DNA strand crosses between the two helices to hold them together.   The double crossover plus junction (DX + J) is very similar to the DX, but the crossover DNA strand has an extra helical section protruding above the plane in which the two adjacent DNA strands exist.   Just as sticky ends allowed branched DNA sections to join, they also combine double crossovers.   The combinining of (DX) and (DX + J) sections is important because the DX portions allow the dispersing of the (DX + J) DNA which contain the extra protrusion above the plane.   Research has shown that gold nanoparticles can link to these protrusions so as to create nanowires.   Thus, the DNA double crossovers serve as "scaffolds" for placing the nanoparticles.   Paul Rothemund at Caltech has demonstrated that a long single strand of DNA can be folded and used as a scaffold to create interesting, programmable shapes.   After folding the long scaffold strand, shorter strands acting are complemented to the scaffold to complete the DNA helix.   The smaller strands are crossovers between sections of the scaffold.   Since DNA crossovers are very sturdy, the smaller strands act as "staples" to hold the scaffold shape together.  
  
  Though still in its infancy, DNA nanotechnology shows potentential in developing nanoelectronic circuits from the bottom-up.   The DNA nanostructures themselves merely serve as high-resolution templates to which electronic components such as carbon nanotubes or nanowires can be linked.   The sticky ends play a key role in systematically placing branched DNA or double crossover elements to form a template for nanocircuits.